US 12,230,676 B2
Nanosheet device with tri-layer bottom dielectric isolation
Xin Miao, San Jose, CA (US); Jingyun Zhang, Albany, NY (US); Alexander Reznicek, Troy, NY (US); and Choonghyun Lee, Chigasaki (JP)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 27, 2021, as Appl. No. 17/449,060.
Prior Publication US 2023/0099214 A1, Mar. 30, 2023
Int. Cl. H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/1083 (2013.01) [H01L 29/0665 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a bottom dielectric isolation disposed above a semiconductor substrate, the bottom dielectric isolation comprising a first portion of a high-k dielectric layer above and in direct mechanical contact with the semiconductor substrate, a spacer material above and in direct mechanical contact with the first portion of the high-k dielectric layer, and a second portion of the high-k dielectric layer above and in direct mechanical contact with the spacer material;
a sequence of semiconductor channel layers stacked perpendicularly to the semiconductor substrate and above the bottom dielectric isolation, the sequence of semiconductor channel layers being separated by and vertically aligned with metal layers of a metal gate stack, each metal layer of the metal gate stack being interior to a respective gate dielectric stack of a sequence of gate dielectric stacks, each metal layer of the metal gate stack comprising one or more work function metals, wherein the second portion of the high-k dielectric layer is in direct mechanical contact with a lowest gate dielectric stack that encloses a lowest metal layer of the metal gate stack;
source/drain regions extending laterally from opposite ends of the semiconductor channel layers, a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate;
an uppermost portion of the metal gate stack disposed between portions of the spacer material perpendicular to the semiconductor substrate; and
a third portion of the high-k dielectric layer below each portion of the spacer material perpendicular to the semiconductor substrate, wherein the metal gate stack disposed between the portions of the spacer material and the third portion of the high-k dielectric layer are above an uppermost semiconductor channel layer of the sequence of semiconductor channel layers.
 
9. A method of forming a semiconductor structure, comprising:
forming a bottom dielectric isolation above a semiconductor substrate, the bottom dielectric isolation comprising a first portion of a high-k dielectric layer above and in direct mechanical contact with the semiconductor substrate, a spacer material above and in direct mechanical contact with the first portion of the high-k dielectric layer, and a second portion of the high-k dielectric layer above and in direct mechanical contact with the spacer material;
forming a sequence of semiconductor channel layers stacked perpendicularly to the semiconductor substrate and above the bottom dielectric isolation, the sequence of semiconductor channel layers being separated by and vertically aligned with metal layers of a metal gate, each metal layer of the metal layer stack being interior to a respective gate dielectric stack of a sequence of gate dielectric stacks, each metal layer of the metal gate stack comprising one or more work function metals, wherein the second portion of the high-k dielectric layer is in direct mechanical contact with a lowest gate dielectric stack that encloses a lowest metal layer of the metal gate stack;
forming source/drain regions extending laterally from opposite ends of the semiconductor channel layers, a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate;
forming an uppermost portion of the metal gate stack disposed between portions of the spacer material perpendicular to the semiconductor substrate; and
forming a third portion of the high-k dielectric layer below each portion of the spacer material perpendicular to the semiconductor substrate, wherein the metal gate stack disposed between the portions of the spacer material and the third portion of the high-k dielectric layer are above an uppermost semiconductor channel layer of the sequence of semiconductor channel layers.
 
17. A semiconductor structure, comprising:
a bottom dielectric isolation disposed above a semiconductor substrate, the bottom dielectric isolation comprising a first portion of a high-k dielectric layer above the semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer, and a second portion of the high-k dielectric layer above the spacer material;
a sequence of semiconductor channel layers stacked perpendicularly to the semiconductor substrate and above the bottom dielectric isolation, the sequence of semiconductor channel layers being separated by and vertically aligned with a metal gate stack;
source/drain regions extending laterally from opposite ends of the semiconductor channel layers, a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate; and
a third portion of the high-k dielectric layer disposed between, and in direct mechanical contact with, the spacer material and an uppermost semiconductor channel layer of the sequence of semiconductor channel layers.