| CPC H01L 29/1045 (2013.01) [H01L 21/046 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7395 (2013.01); H01L 29/7802 (2013.01)] | 13 Claims |

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1. A silicon carbide (SiC) planar transistor device comprising:
a SiC semiconductor substrate of a first charge type having a top surface and a bottom surface;
a SiC epitaxial layer of the first charge type formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
a source structure of the first charge type formed in the top surface of the SiC epitaxial layer, the source structure having a top surface;
a drain structure of the first charge type formed on the bottom surface of the SiC semiconductor substrate;
a gate structure comprising a gate dielectric and a gate runner, wherein the gate dielectric covers at least part of the source structure and the gate runner;
a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure, wherein a doping profile of the second charge type of the channel region comprises a first region and a second region;
wherein the first region has a constant doping concentration in a range of 2×1017 cm-3 to 3×1018 cm−3 and is located in a vertical direction below to the gate dielectric with a depth between 50 nm to 250 nm from the top surface of the SiC epitaxial layer;
wherein the second region has a Pearson-Type-IV-like distributed doping concentration with a peak doping concentration in a range of 1.5×108 cm−3 to 8×1018 cm−3 and is located in a vertical direction below and adjacent to the first region with the peak position of the Pearson-Type-IV-like distribution in a range of 300 nm to 500 nm from the top surface of the SiC epitaxial layer; and
wherein the channel has a length in a range of 50 nm to 250 nm.
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