US 12,230,674 B2
Radiation hardened high voltage superjunction MOSFET
Kiraneswar Muthuseenu, Tempe, AZ (US); Samuel Anderson, Tempe, AZ (US); and Takeshi Ishiguro, Fukushima (JP)
Assigned to IceMos Technology Limited, (GB)
Filed by IceMos Technology Limited, Belfast (GB)
Filed on Jul. 25, 2023, as Appl. No. 18/358,282.
Application 18/358,282 is a division of application No. 17/804,491, filed on May 27, 2022, granted, now 11,757,001.
Application 17/804,491 is a continuation of application No. 16/934,738, filed on Jul. 21, 2020, granted, now 11,362,179, issued on Jun. 14, 2022.
Prior Publication US 2023/0369403 A1, Nov. 16, 2023
Int. Cl. H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01)
CPC H01L 29/0847 (2013.01) [H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 29/4236 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 21/26513 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a semiconductor layer;
a first trench formed through the semiconductor layer;
a second trench formed through the semiconductor layer;
a plug region formed within the semiconductor layer and extending between the first trench and second trench;
a body region formed within the plug region;
a source/drain region formed within the plug region, wherein a width of the source/drain region across the semiconductor layer is less than a width of the plug region and a width of the body region across the semiconductor layer is less than a width of the source/drain region;
a gate trench formed adjacent to the source/drain region and body region and extending into the semiconductor layer;
a dielectric layer disposed within the gate trench; and
a trench gate electrode disposed within the gate trench.