US 12,230,673 B2
Field-effect transistors having a gate electrode positioned inside a substrate recess
Michel Abou-Khalil, Essex Junction, VT (US); Steven M. Shank, Jericho, VT (US); Aaron Vallett, Jericho, VT (US); Sarah McTaggart, Essex Junction, VT (US); and Rajendran Krishnasamy, Essex Junction, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Mar. 30, 2022, as Appl. No. 17/708,561.
Prior Publication US 2023/0317776 A1, Oct. 5, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 29/1087 (2013.01); H01L 29/4236 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a semiconductor substrate including a first surface, a first recess in the first surface, and a second surface inside the first recess;
a shallow trench isolation region extending from the first surface into the semiconductor substrate, the shallow trench isolation region positioned to surround an active device region including the first recess; and
a field-effect transistor including a gate electrode positioned on a portion of the second surface and a gate dielectric layer on the second surface, the gate dielectric layer positioned between the gate electrode and the portion of the second surface, and the gate dielectric layer including a first section with a first thickness and a second section with a second thickness that is greater than the first thickness.