| CPC H01L 28/91 (2013.01) [H01G 4/30 (2013.01); H01L 21/76832 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01)] | 20 Claims |
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12. A method for manufacturing a stacked capacitor structure, comprising:
forming a first patterned structure over a substrate;
forming a first bottom electrode over the first patterned structure;
depositing a first dielectric film over the first bottom electrode;
depositing a first top electrode layer over the first dielectric film;
forming a first sidewall spacer and a first vertical interconnect structure which extend from the first bottom electrode, wherein the first vertical interconnect structure is isolated from the first top electrode layer by the first sidewall spacer;
forming a second patterned structure over the first top electrode layer;
forming a second bottom electrode over the second patterned structure, wherein the second bottom electrode is electrically connected to the first bottom electrode through the first vertical interconnect structure;
depositing a second dielectric film over the second bottom electrode;
depositing a second top electrode layer over the second dielectric film; and
forming a second vertical interconnect structure extending from the first top electrode layer, wherein the second top electrode layer is electrically connected to the first top electrode layer through the second vertical interconnect structure.
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