US 12,230,649 B2
AI system on chip (SOC) for robotics vision applications
James E. Retterath, Excelsior, MN (US)
Assigned to Vergence Automation, Inc., Excelsior, MN (US)
Filed by Vergence Automation, Inc., Excelsior, MN (US)
Filed on May 19, 2021, as Appl. No. 17/324,964.
Claims priority of provisional application 63/027,227, filed on May 19, 2020.
Prior Publication US 2021/0366952 A1, Nov. 25, 2021
Int. Cl. H01L 27/144 (2006.01); G06F 9/30 (2018.01); G06N 5/04 (2023.01); H01L 27/146 (2006.01)
CPC H01L 27/1446 (2013.01) [G06F 9/30101 (2013.01); G06N 5/04 (2013.01); H01L 27/14643 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A sub-frame imaging pixel comprising:
a photodetector;
photodetector control circuitry (PDC) comprising (i) at least three analog storage elements configured to store at least three sub-frames, wherein each of the at least three sub-frames includes analog data transferred from the photodetector, and (ii) a PDC instruction bus coupled to each of the at least three sub-frames and configured to control operations of the PDC on said analog data transferred from the photodetector; and
an analog pixel processor (APP) configured to process neighbor-in-space and neighbor-in-time functions on said analog data stored in the at least three sub-frames, the APP comprising:
at least two banks of analog registers configured to: (i) receive the analog data from the PDC, and (ii) perform (a) data transfer operations, and (b) one or more of math operations and logic operations on the analog data stored in the at least two banks of analog registers,
a compare-and-flag functional block for each of the at least two banks of analog registers, wherein write operations to a register amongst the at least two banks of analog registers are executed when a signal is active during a register write cycle,
north, east, west, and south (NEWS) registers configured to perform the data transfer operations between neighboring sub-frame imaging pixels to facilitate the neighbor-in-space functions on the analog data stored in the at least two banks of analog registers, and
an APP instruction bus that is separate and distinct from the PDC instruction bus and is configured to: (i) allow for concurrent processing of the analog data stored in two sub-frames of the at least three sub-frames, and (ii) execute each of the following: (a) the data transfer operations, (b) the math operations, (c) the logic operations, (d) the neighbor-in-space functions, and (e) the neighbor-in-time functions.