US 12,230,648 B2
Display substrate, manufacturing method thereof and display apparatus
Hao Luo, Beijing (CN); Bo Wu, Beijing (CN); Dongmei Wei, Beijing (CN); Yin Deng, Beijing (CN); Zhengdong Zhang, Beijing (CN); and Yao Li, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/915,173
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Oct. 28, 2021, PCT No. PCT/CN2021/127038
§ 371(c)(1), (2) Date Sep. 28, 2022,
PCT Pub. No. WO2022/127396, PCT Pub. Date Jun. 23, 2022.
Claims priority of application No. 202011500714.0 (CN), filed on Dec. 18, 2020; and application No. 202110710158.8 (CN), filed on Jun. 25, 2021.
Prior Publication US 2023/0123019 A1, Apr. 20, 2023
Int. Cl. G02F 1/1343 (2006.01); G02F 1/1333 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/167 (2019.01); G02F 1/1676 (2019.01); G02F 1/1685 (2019.01); H01L 27/12 (2006.01)
CPC H01L 27/1288 (2013.01) [G02F 1/133345 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 1/167 (2013.01); G02F 1/1676 (2019.01); G02F 1/1685 (2019.01); H01L 27/1255 (2013.01); G02F 1/134309 (2013.01)] 18 Claims
OG exemplary drawing
 
9. A display substrate having a plurality of pixels, wherein in at least one of the plurality of pixels, the display substrate comprises:
a base substrate;
a thin film transistor on the base substrate and comprising a gate electrode, a source electrode and a drain electrode;
a first auxiliary electrode, a second auxiliary electrode and a pixel electrode sequentially arranged on the base substrate, wherein orthographic projections of the first auxiliary electrode, the second auxiliary electrode and the pixel electrode on the base substrate at least partially overlap each other;
a first interlayer insulating layer between a layer where the first auxiliary electrode is located and a layer where the second auxiliary electrode is located, such that the first auxiliary electrode is insulated from the second auxiliary electrode; and
a second interlayer insulating layer between the layer where the second auxiliary electrode is located and a layer where the pixel electrode is located, such that the second auxiliary electrode is insulated from the pixel electrode; wherein
the source electrode and the drain electrode of the thin film transistor and the second auxiliary electrode are arranged in a same layer and are made of a same material; the pixel electrode is connected to the drain electrode of the thin film transistor through a second via extending through the second interlayer insulating layer, and the pixel electrode is electrically connected to the first auxiliary electrode through a first via extending through the first interlayer insulating layer and the second interlayer insulating layer;
wherein where an operating frequency band of the pixels is a first preset frequency band, a length of each of the source electrode and the drain electrode of the thin film transistor is a first distance L1; an area of the second auxiliary electrode is a first area S1;
where the operating frequency band of the pixels is a second preset frequency band, a length of each of the source electrode and the drain electrode of the thin film transistor is a second distance L2; an area of the second auxiliary electrode is a second area S2; and
where the operating frequency band of the pixels is a third preset frequency band, a length of each of the source electrode and the drain electrode of the thin film transistor is a third distance L3; an area of the second auxiliary electrode is a third area S3; and
wherein a maximum frequency value in the first preset frequency band is less than a minimum frequency value in the second preset frequency band, and a maximum frequency value in the second preset frequency band is less than a minimum frequency value in the third preset frequency band; L3<L2<L1; S3<S2<S1.