| CPC H01L 27/1248 (2013.01) | 17 Claims |
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1. An array substrate, comprising a substrate, a gate, a gate insulating layer, an oxide semiconductor layer, and a source-drain metal layer, wherein the gate, the gate insulating layer, the oxide semiconductor layer, and the source-drain metal layer are disposed on the substrate, the gate insulating layer is disposed between the gate and the oxide semiconductor layer, and the gate, the gate insulating layer, the oxide semiconductor layer, and the source-drain metal layer are sequentially stacked in a direction away from the substrate;
wherein material of the oxide semiconductor layer comprises an oxide of a first metal element, material of at least a portion of the gate insulating layer in contact with the oxide semiconductor layer comprises the oxide of the first metal element, and the first metal element comprises one of aluminum, hafnium, titanium, zirconium, praseodymium, and lanthanum; and
wherein the oxide semiconductor layer further comprises an oxide of a second metal element and an oxide of a third metal element, the first metal element is aluminum (Al), the second metal element is gallium (Ga), the third metal element is zinc (Zn), and molar contents of the aluminum (Al), the gallium (Ga), and the zinc (Zn) satisfy following relationships:
0.1≤Al/(Al+Ga+Zn)≤0.5;
0.2≤Ga/(Al+Ga+Zn)≤0.4;
0.3≤Zn/(Al+Ga+Zn)≤0.5.
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