| CPC H01L 27/1244 (2013.01) [G02F 1/134363 (2013.01); G02F 1/136227 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); H01L 27/1225 (2013.01)] | 15 Claims |
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1. A thin film transistor array panel, comprising:
a substrate;
a transistor comprising a drain electrode and a source electrode
an organic insulating layer disposed on the drain electrode and having a first contact hole;
a common electrode disposed on the organic insulating layer and having a second contact hole;
a passivation layer disposed on the common electrode and having a third contact hole; and
a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode, wherein
a region in which the drain electrode and the pixel electrode contact each other overlaps the third contact hole,
wherein the third contact hole is smaller than the first contact hole, and wherein the passivation layer includes a flat portion disposed on an upper surface of the drain electrode, and
a width of a region in which the drain electrode and the pixel electrode contact each other is smaller than an entire width defining the third contact hole, and
side surfaces of the organic insulating layer defining the first contact hole directly contact the passivation layer on both sides of the first contact hole,
wherein the pixel electrode is disposed on only one side of the both sides of the first contact hole.
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