US 12,230,635 B2
Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach
Nicole Thomas, Portland, OR (US); Ehren Mannebach, Beaverton, OR (US); Cheng-Ying Huang, Portland, OR (US); and Marko Radosavljevic, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 17, 2023, as Appl. No. 18/513,028.
Application 18/513,028 is a continuation of application No. 17/731,110, filed on Apr. 27, 2022, granted, now 11,862,636.
Application 17/731,110 is a continuation of application No. 16/912,113, filed on Jun. 25, 2020, granted, now 11,348,919, issued on May 31, 2022.
Prior Publication US 2024/0088153 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0922 (2013.01) [H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/823807 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 26 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a substrate, the vertical arrangement of nanowires having an active nanowire above a silicon oxide nanowire;
a first gate stack over and around the active nanowire, the first gate stack having a first gate electrode; and
a second gate stack over and around the silicon oxide nanowire, the second gate stack having a second gate electrode in contact with and distinct from the first gate electrode.