US 12,230,633 B2
Integrated circuit structure including multi-width semiconductor fins
Jhon-Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,764.
Application 18/362,764 is a division of application No. 17/353,552, filed on Jun. 21, 2021, granted, now 11,791,337.
Application 17/353,552 is a continuation of application No. 16/726,005, filed on Dec. 23, 2019, granted, now 11,043,490, issued on Jun. 22, 2021.
Application 16/726,005 is a continuation of application No. 15/924,262, filed on Mar. 18, 2018, granted, now 10,515,954, issued on Dec. 24, 2019.
Prior Publication US 2023/0378177 A1, Nov. 23, 2023
Int. Cl. H01L 27/08 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01)
CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0207 (2013.01); H01L 29/0692 (2013.01); H01L 29/66545 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/7853 (2013.01); H01L 29/7855 (2013.01); H01L 29/7856 (2013.01); H10B 12/056 (2023.02); H10B 12/36 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a first circuit comprising a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin;
a second circuit comprising a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin; and
a third circuit comprising a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin,
wherein the first gate dielectric layer has a thickness greater than a thickness of the second gate dielectric layer, and the third semiconductor fin has a width less than a width of the second semiconductor fin.