| CPC H01L 27/0886 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823456 (2013.01)] | 20 Claims |
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1. A method, comprising:
forming a first active region and a second active region over a substrate and extending along a first direction, wherein the first active region and the second active region are separated by an isolation structure;
forming a first gate structure over the first active region;
forming a plurality of second gate structures over the second active region, the plurality of second gate structures being arranged along the first direction and separated from each other, and wherein along the first direction, a sum of gate lengths of the second gate structures is n times a gate length of the first gate structure, and n is a positive integer and is greater than 1, and wherein each of the gate lengths of the second gate structures is the same as the gate length of the first gate structure, wherein the plurality of second gate structures collectively serve as a gate of a same transistor, wherein the second active region has a portion between the second gate structures, and the portion of the second active region between the second gate structures is free of a source/drain region;
forming first source/drain regions in the first active region; and
forming second source/drain regions in the second active region, wherein portions of the second active region between two adjacent second gate structures have lower dopant concentrations than the second source/drain regions.
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5. A method for forming an integrated circuit (IC) structure, comprising:
forming a first active region and a second active region over a substrate;
forming a first gate over the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region; and
forming a second gate over the second active region and comprising a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1, and wherein a first set of the gate structures of the second gate have a first gate length, the first gate length is m times the first effective gate length, a second set of the gate structures have a second gate length, the second gate length is o times the first effective gate length, wherein m and o are different positive integers, wherein the first set of the gate structures and the second set of the gate structures are of a single transistor.
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14. A method for forming an integrated circuit (IC) structure, comprising:
forming a first transistor, comprising:
forming a first active region and a second active region over a substrate, wherein the first and second active regions extend along a first direction;
forming an isolation structure over the substrate and separating the first active region from the second active region;
forming a gate having gate structures disposed on the first and second active regions, respectively, wherein along the first direction, an effective gate length of the gate is n times a critical dimension of a technology node of the first transistor, and n is a positive integer and is greater than 1, wherein the gate structures are separated from each other and are electrically connected to a same voltage node, wherein the gate structures are of the same first transistor, wherein there is no source/drain region in a portion of the first active region between adjacent two of the gate structures;
forming gate spacers on sidewalls of each of the gate structures of the gate;
forming a first source/drain region in the first active region; and
forming a second source/drain region in the second active region; and
forming a second transistor having a gate length substantially equal to the critical dimension of the technology node of the first transistor.
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