US 12,230,627 B2
Semiconductor device
Isao Saito, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed by FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed on Jul. 21, 2021, as Appl. No. 17/381,426.
Application 17/381,426 is a continuation of application No. PCT/JP2020/025212, filed on Jun. 26, 2020.
Claims priority of application No. 2019-144555 (JP), filed on Aug. 6, 2019.
Prior Publication US 2021/0351177 A1, Nov. 11, 2021
Int. Cl. H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0629 (2013.01) [H01L 23/5286 (2013.01); H01L 27/0222 (2013.01); H01L 27/0274 (2013.01); H01L 29/7805 (2013.01); H01L 29/7813 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first line configured to receive a power supply voltage;
a second line configured to be coupled to a load of the semiconductor device;
first and second metal-oxide-semiconductor (MOS) transistors coupled in series between the first line and the second line, each of the first and second MOS transistors having a drain electrode and a gate electrode, the drain electrode of the first MOS transistor being coupled to the drain electrode of the second MOS transistor;
a third line coupled to the gate electrode of the first MOS transistor;
a fourth line coupled to the gate electrode of the second MOS transistor, the third and fourth lines being electrically separated from each other;
a charge pump circuit configured to output a predetermined voltage in response to a first instruction signal; and
a separation circuit configured to receive the predetermined voltage from the charge pump circuit, and to apply the predetermined voltage to both the third line and the fourth line, but separately, to turn on the first and second MOS transistors.