US 12,230,626 B2
Transistor
Toshinari Sasaki, Minato-ku (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Dec. 12, 2023, as Appl. No. 18/536,767.
Application 18/536,767 is a continuation of application No. 17/881,106, filed on Aug. 4, 2022, granted, now 11,887,980.
Application 17/881,106 is a continuation of application No. 16/845,289, filed on Apr. 10, 2020, granted, now 11,437,363, issued on Sep. 6, 2022.
Application 16/845,289 is a continuation of application No. PCT/JP2018/033031, filed on Sep. 6, 2018.
Claims priority of application No. 2017-203812 (JP), filed on Oct. 20, 2017.
Prior Publication US 2024/0128259 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); G09G 3/20 (2006.01); H01L 23/482 (2006.01); H01L 23/485 (2006.01); H01L 27/02 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/861 (2006.01); H01L 29/872 (2006.01); H01L 29/24 (2006.01)
CPC H01L 27/0255 (2013.01) [G09G 3/20 (2013.01); H01L 23/482 (2013.01); H01L 23/485 (2013.01); H01L 29/42376 (2013.01); H01L 29/45 (2013.01); H01L 29/66969 (2013.01); H01L 29/7391 (2013.01); H01L 29/861 (2013.01); H01L 29/872 (2013.01); G09G 2300/0885 (2013.01); G09G 2330/04 (2013.01); G09G 2330/08 (2013.01); H01L 29/0688 (2013.01); H01L 29/0692 (2013.01); H01L 29/24 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A transistor comprising:
a semiconductor layer including a first region and a second region;
a first insulating layer covering the semiconductor layer;
a gate electrode;
a first conductive layer arranged above the first insulating layer; and
a second conductive layer arranged above the first insulating layer; and
wherein
a first aperture is formed in the first insulating layer overlapped with the first region,
a second aperture is formed in the first insulating layer overlapped with the second region,
a resistance of the semiconductor layer in the second region is different from a resistance of the semiconductor layer in the first region,
the gate electrode overlaps the first region of the semiconductor layer,
the first conductive layer connects to the semiconductor layer in the first aperture and overlapping with the semiconductor layer in the first region in a planar view,
the second conductive layer connects to the semiconductor layer in the second aperture,
a boundary between the first region and the second region is along a part of a pattern end of the first conductive layer in a planar view.