US 12,230,622 B2
Electronic device with stacked printed circuit boards
Ya-Lun Yang, Hsinchu (TW); Wen-Chou Wu, Hsinchu (TW); and Che-Hung Kuo, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Sep. 7, 2022, as Appl. No. 17/938,965.
Claims priority of provisional application 63/255,028, filed on Oct. 13, 2021.
Prior Publication US 2023/0110957 A1, Apr. 13, 2023
Int. Cl. H05K 1/14 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01); H05K 1/18 (2006.01); H01L 23/00 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 23/3128 (2013.01); H01L 23/367 (2013.01); H01L 23/49811 (2013.01); H01L 23/5383 (2013.01); H01L 23/5389 (2013.01); H05K 1/145 (2013.01); H05K 1/181 (2013.01); H01L 24/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a main printed circuit board (PCB) assembly comprising a bottom PCB and a semiconductor package mounted on an upper surface of the bottom PCB, wherein the semiconductor package comprises a substrate and a semiconductor die mounted on a top surface of the substrate, wherein the semiconductor die and the top surface of the substrate are encapsulated by a molding compound, wherein the semiconductor die has an active surface and a rear surface coupled to the top surface of the substrate, wherein the semiconductor die comprises through silicon vias;
a top PCB mounted on the semiconductor package through first connecting elements, wherein the top PCB only overlaps with a peripheral region of a top surface of the semiconductor package; and
a middle re-distribution layer (RDL) structure disposed between the semiconductor die and the top PCB, wherein the active surface of the semiconductor die is directly connected to the middle RDL structure through second connecting elements, wherein the middle RDL structure comprises dielectric layers and interconnect structures.