US 12,230,610 B2
Double-sided substrate with cavities for direct die-to-die interconnect
Pooya Tadayon, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 6, 2023, as Appl. No. 18/377,639.
Application 18/377,639 is a continuation of application No. 16/524,743, filed on Jul. 29, 2019, granted, now 11,817,423.
Prior Publication US 2024/0038729 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/13 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/13 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 25/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06589 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a package substrate having an opening therein;
a first die and a second die in the opening in the package substrate, the first die over and coupled to the second die, wherein a footprint of the first die only partially overlaps a footprint of the second die, wherein a first portion of the package substrate is vertically over and coupled to the second die, wherein a second portion of the package substrate is vertically beneath and coupled to the first die, wherein the first die is coupled to the second portion of the package substrate by first interconnects, wherein the second die is coupled to the first portion of the package substrate by second interconnects, wherein the first die is coupled to the second die by third interconnects, the third interconnects on a same side of the first die as the first interconnects, and wherein the second die is coupled to the first die by fourth interconnects, the fourth interconnects on a same side of the second die as the second interconnects.