US 12,230,603 B2
Method of fabricating a semiconductor chip having strength adjustment pattern in bonding layer
Hong-Wei Chan, Hsinchu (TW); Jiing-Feng Yang, Hsinchu County (TW); Yung-Shih Cheng, Hsinchu (TW); Yao-Te Huang, Hsinchu (TW); and Hui Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,825.
Application 18/359,825 is a continuation of application No. 17/213,162, filed on Mar. 25, 2021, granted, now 11,756,924.
Prior Publication US 2023/0369285 A1, Nov. 16, 2023
Int. Cl. H01L 21/78 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01)
CPC H01L 24/94 (2013.01) [H01L 21/768 (2013.01); H01L 21/7806 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor chip, comprising:
form a first bonding layer on a first wafer substrate, the first bonding layer having a recess;
forming a circuitry structure and a second bonding layer on a second wafer substrate, the circuitry structure being located between the second wafer substrate and the second bonding layer;
bonding the second wafer substrate to the first wafer substrate by contacting the second bonding layer with the first bonding layer;
removing the second wafer substrate;
forming a conductor terminal on the circuitry structure, wherein the conductor terminal is positioned in a component region keeping from the recess of the first bonding layer; and
performing a singulation process to obtain a semiconductor chip comprising the circuitry structure and the conductor terminal, wherein the recess is separated from the semiconductor chip by the singulation process.