US 12,230,584 B2
Method for manufacturing semiconductor mark, and semiconductor mark
Chuang Shan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 25, 2022, as Appl. No. 17/648,878.
Application 17/648,878 is a continuation of application No. PCT/CN2021/106577, filed on Jul. 15, 2021.
Claims priority of application No. 202110016542.8 (CN), filed on Jan. 7, 2021.
Prior Publication US 2022/0216163 A1, Jul. 7, 2022
Int. Cl. H01L 23/544 (2006.01); G03F 1/36 (2012.01)
CPC H01L 23/544 (2013.01) [G03F 1/36 (2013.01); H01L 2223/54426 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing semiconductor mark, comprising:
providing a pattern having a peripheral edge corrected by Optical Proximity Correction (OPC);
cutting a plurality of independent alignment sections from the pattern; and
splicing the plurality of alignment sections to form a semiconductor mark having a peripheral edge corrected by OPC;
wherein the plurality of alignment sections each comprises an original edge corrected by OPC and a cutting edge not corrected by OPC, wherein the cutting edges of the plurality of alignment sections are spliced to form the semiconductor mark; and
wherein an area of the semiconductor mark is smaller than that of the pattern.