US 12,230,583 B2
Interposers for microelectronic devices
Owen Fay, Meridian, ID (US); and Chan H. Yoo, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 17, 2023, as Appl. No. 18/381,061.
Application 18/381,061 is a continuation of application No. 17/682,734, filed on Feb. 28, 2022, granted, now 11,824,010.
Application 17/682,734 is a continuation of application No. 16/696,423, filed on Nov. 26, 2019, granted, now 11,264,332.
Claims priority of provisional application 62/772,291, filed on Nov. 28, 2018.
Prior Publication US 2024/0120283 A1, Apr. 11, 2024
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/8234 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/823475 (2013.01); H01L 23/147 (2013.01); H01L 23/5383 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 25/18 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/2518 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/1443 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an interposer including,
a core comprising a non-organic semiconductor material;
a first group of redistribution layers formed over a first side of the core;
a second group of redistribution layers formed over a second side of the core; and
multiple contacts extending through the core;
the interposer having a first surface including multiple arrays of contacts for establishing contact with respective semiconductor device structures,
the multiple arrays of contacts including,
at least first and second arrays of contacts each configured for establishing electrical communication with a respective stack of memory die, and
a third array of contacts configured for establishing electrical communication with an additional semiconductor device structure;
wherein the core includes multiple doped regions of the non-organic semiconductor material, the doped regions forming respective bodies of active circuit elements, and multiple doped regions of the non-organic semiconductor material forming respective bodies of one or more passive circuit elements;
wherein each redistribution layer comprises a dielectric material supporting a conductive material; and
wherein at least one active circuit element having a body formed in the non-organic semiconductor material is electrically coupled to a conductive material of a redistribution layer in one of the first and second groups of redistribution layers.