US 12,230,581 B2
Multi-device graded embedding package substrate and manufacturing method thereof
Xianming Chen, Guangdong (CN); Lei Feng, Guangdong (CN); Benxia Huang, Guangdong (CN); and Yejie Hong, Guangdong (CN)
Assigned to Zhuhai ACCESS Semiconductor Co., Ltd., Guangdong (CN)
Filed by Zhuhai ACCESS Semiconductor Co., Ltd, Guangdong (CN)
Filed on May 11, 2022, as Appl. No. 17/741,649.
Claims priority of application No. 202110533782.5 (CN), filed on May 14, 2021.
Prior Publication US 2022/0367373 A1, Nov. 17, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2221/6835 (2013.01); H01L 2224/214 (2013.01); H01L 2224/215 (2013.01); H01L 2924/01029 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for manufacturing a multi-device graded embedding package substrate, the method comprising:
(a) preparing an organic matrix substrate, wherein the organic matrix substrate comprises a first conductive copper pillar layer and a first loop-back strip-shaped copper pillar layer penetrating through the organic matrix substrate, the first loop-back strip-shaped copper pillar layer comprising at least one loop-back strip-shaped copper pillar;
(b) etching one loop-back strip-shaped copper pillar in the first loop-back strip-shaped copper pillar layer and removing dielectric material from it to form a first device cavity to prepare a first dielectric layer;
(c) attaching the first device on a bottom of the first device cavity, and forming a first packaging layer on an upper surface of the first dielectric layer and in a gap between the first device and the first device cavity;
(d) forming a first wiring layer on the first packaging layer and forming a second wiring layer on the first dielectric layer so that the first wiring layer and the second wiring layer are conductively connected through the first conductive copper pillar layer, wherein a terminal of the first device is conductively connected to the second wiring layer, and a back surface of the first device is connected to the first wiring layer;
(e) forming a second conductive copper pillar layer, a heat dissipation copper block layer, and a second loop-back strip-shaped copper pillar layer on the first wiring layer, and forming a third conductive copper pillar layer and a third loop-back strip-shaped copper pillar layer on the second wiring layer so that the first device and the heat dissipation copper block layer are connected via the first wiring layer, and the second loop-back strip-shaped copper pillar layer and the third loop-back strip-shaped copper pillar layer respectively longitudinally coincide with the first loop-back strip-shaped copper pillar layer;
(f) laminating a dielectric material above and below the first dielectric layer, thinning the dielectric material, exposing ends of the second conductive copper pillar layer, the heat dissipation copper pillar layer, and the second loop-back strip-shaped copper pillar layer to form a second dielectric layer, and exposing ends of the third conductive copper pillar layer and the third loop-back strip-shaped copper pillar layer to form a third dielectric layer;
(g) simultaneously etching the loop-back strip-shaped copper pillars of the first loop-back strip-shaped copper pillar layer, the second loop-back strip-shaped copper pillar layer, and the third loop-back strip-shaped copper pillar layer longitudinally at the same position, and removing the dielectric material in the loop-back strip-shaped copper pillar to form a second device cavity;
(h) attaching a second device on the bottom of the second device cavity, and forming a second packaging layer on the upper surface of the second dielectric layer and in the gap between the second device and the second device cavity; and
(i) forming a third wiring layer on the second packaging layer, and a fourth wiring layer on the third dielectric layer so that the first wiring layer and the third wiring layer are conductively connected via the second conductive copper pillar layer and the heat dissipation copper block layer, the second wiring layer and the fourth wiring layer are conductively connected via the third conductive copper pillar layer, the terminal of the second device is conductively connected to the fourth wiring layer, and the back surface of the second device is conductively connected the third wiring layer.