US 12,230,577 B2
Local density control for metal capacitance reduction
Burak Baylav, Hillsboro, OR (US); and Dhananjay Bhawe, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,947.
Prior Publication US 2022/0415812 A1, Dec. 29, 2022
Int. Cl. H01L 23/538 (2006.01); G06F 30/392 (2020.01); H01L 23/522 (2006.01)
CPC H01L 23/5386 (2013.01) [G06F 30/392 (2020.01); H01L 23/5222 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An integrated circuit structure comprising:
a plurality of interconnect lines; and
a plurality of dummy lines co-planar with the plurality of interconnect lines, wherein a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions of approximately equal area within a rectangular grid array.