US 12,230,574 B2
Reducing RC delay in semiconductor devices
Gulbagh Singh, Tainan (TW); Kun-Tsang Chuang, Miaoli (TW); and Po-Jen Wang, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,560.
Application 17/745,509 is a division of application No. 16/849,709, filed on Apr. 15, 2020, granted, now 11,335,638, issued on May 17, 2022.
Application 18/361,560 is a continuation of application No. 17/745,509, filed on May 16, 2022, granted, now 11,804,439.
Prior Publication US 2023/0378071 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/535 (2006.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/482 (2006.01); H01L 23/485 (2006.01); H01L 27/12 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/743 (2013.01); H01L 21/76802 (2013.01); H01L 21/7682 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/4821 (2013.01); H01L 23/485 (2013.01); H01L 23/5222 (2013.01); H01L 23/5223 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 27/1203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first dielectric layer over a transistor;
forming a second dielectric layer on the first dielectric layer;
forming a contact structure through the first and second dielectric layers, wherein the contact structure is in contact with the transistor;
forming a first cavity in the first dielectric layer and adjacent to the contact structure;
forming a second cavity in the second dielectric layer and above the first cavity; and
forming a liner on a first inner surface of the first cavity and on a second inner surface of the second cavity.