| CPC H01L 23/535 (2013.01) [H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
a lower structure including
a semiconductor substrate,
a circuit element on the semiconductor substrate,
a circuit interconnection structure on the semiconductor substrate, the circuit interconnection structure including a plurality of connection patterns on different levels and electrically connected to the circuit element, and
a lower insulating structure covering the circuit element and the circuit interconnection structure;
an upper structure including
an upper substrate in contact with an upper surface of the lower insulating structure,
a stack structure on the upper substrate, the stack structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and
a vertical memory structure penetrating through the stack structure in the vertical direction; and
a contact plug penetrating through at least a portion of the lower insulating structure such that the contact plug contacts an uppermost connection pattern, among the plurality of connection patterns,
wherein the lower insulating structure includes a first insulating layer, a capping layer and a second insulating layer sequentially stacked in a region between the upper substrate and the uppermost connection pattern, and
the capping layer includes a material different from a material of the first insulating layer and a material of the second insulating layer.
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