US 12,230,571 B2
Integrated circuit devices including a power rail and methods of forming the same
Gilhwan Son, Clifton Park, NY (US); Hoonseok Seo, Niskayuna, NY (US); Saehan Park, Clifton Park, NY (US); Byounghak Hong, Albany, NY (US); and Kang-Ill Seo, Springfield, VA (US)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 14, 2022, as Appl. No. 17/576,007.
Claims priority of provisional application 63/282,411, filed on Nov. 23, 2021.
Prior Publication US 2023/0163073 A1, May 25, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/48 (2006.01); H01L 23/485 (2006.01); H01L 23/535 (2006.01); H01L 27/088 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/76898 (2013.01); H01L 23/535 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit device, the method comprising:
forming a transistor on a first surface of a substrate, wherein the transistor comprises an active region, a source/drain region contacting the active region and a gate electrode on the active region;
forming an etch stop layer contacting the first surface of the substrate;
forming a conductive wire that is electrically connected to the source/drain region;
forming a trench extending through the substrate by etching a second surface of the substrate, wherein the second surface of the substrate is opposite the first surface of the substrate; and
forming a power rail in the trench, wherein the power rail is electrically connected to conductive wire.