US 12,230,569 B2
Apparatus and method to increase effective capacitance with layout staples
Kushal Sreedhar, Portland, OR (US); Christopher Mozak, Portland, OR (US); and Mahmoud Elassal, King City, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 16, 2021, as Appl. No. 17/177,055.
Prior Publication US 2021/0167014 A1, Jun. 3, 2021
Int. Cl. H01L 23/528 (2006.01); H01L 23/522 (2006.01); G11C 5/14 (2006.01); G11C 11/16 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); G11C 5/14 (2013.01); G11C 11/1697 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first metal layer comprising a first plurality of tracks, wherein the first plurality of tracks extends in a first direction and includes a first supply rail and a first ground rail;
a second metal layer comprising a second plurality of tracks, wherein the second plurality of tracks extends in a second direction and includes a second supply rail and a second ground rail, wherein the first direction is orthogonal to the second direction;
a set of metal layers between the first metal layer and the second metal layer, wherein the set of metal layers are configured as metal-insulator-metal capacitors; and
a plurality of staples or stubs uniformly spread in a region over the set of metals layers, the plurality of staples or stubs in contact with the second supply rail and extending under the second ground rail,
wherein the first plurality of tracks includes a third supply rail, the plurality of staples or stubs in contact with the third supply rail and extending under the second ground rail.