US 12,230,567 B2
Semiconductor structure and manufacturing method thereof
Wei-Ren Wang, New Taipei (TW); Tze-Liang Lee, Hsinchu (TW); and Jen-Hung Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/461,166.
Prior Publication US 2023/0068625 A1, Mar. 2, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76826 (2013.01); H01L 21/76832 (2013.01); H01L 21/76877 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first conductive feature and a second conductive feature in a dielectric layer;
selectively forming a first etch stop layer over the dielectric layer while leaving the first conductive feature and the second conductive feature exposed;
forming a capping layer over the first conductive feature;
performing a plasma treatment on the capping layer to form a bonding layer between the capping layer and the first conductive feature;
forming a second etch stop layer over the first etch stop layer;
etching the second etch stop layer to form an opening; and
filling a conductive material in the opening to form a conductive via.