US 12,230,565 B2
Integrated filler capacitor cell device and corresponding manufacturing method
Abderrezak Marzaki, Aix en Provence (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Feb. 9, 2024, as Appl. No. 18/437,720.
Application 18/116,672 is a division of application No. 17/173,275, filed on Feb. 11, 2021, granted, now 11,621,222.
Application 18/437,720 is a continuation of application No. 18/116,672, filed on Mar. 2, 2023, granted, now 11,935,828.
Application 17/173,275 is a continuation in part of application No. 16/242,529, filed on Jan. 8, 2019, granted, now 10,943,862.
Claims priority of application No. 1850157 (FR), filed on Jan. 9, 2018.
Prior Publication US 2024/0186236 A1, Jun. 6, 2024
Int. Cl. H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 23/522 (2006.01); H01L 27/08 (2006.01)
CPC H01L 23/5223 (2013.01) [H01L 21/76224 (2013.01); H01L 27/0805 (2013.01); H01L 29/66181 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method, comprising:
forming an isolating region delimiting a working area of a first semiconductor region;
etching at least one trench in said working area;
filling the at least one trench with an electrically conductive central portion insulated from bottom and sides of said at least one trench by an isolating layer;
forming a cover region which covers at least a first part of said filled at least one trench, said cover region comprising at least one dielectric layer in contact with said filled at least one trench;
siliciding at least the electrically conductive central portion of a second part of said at least one trench which is not covered by the cover region;
making a first electrical contact to the first semiconductor region so as to form a first electrode of a filler capacitor cell device; and
making a second electrical contact to the silicided electrically conductive central portion so as to form a second electrode of the filler capacitor cell device.