	US 12,230,560 B2
	Semiconductor package structure
Che-Hung Kuo, Hsinchu (TW); Hsing-Chih Liu, Hsinchu (TW); and Tai-Yu Chen, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsinchu (TW)
Filed on Dec. 9, 2021, as Appl. No. 17/546,191.
Claims priority of provisional application 63/135,020, filed on Jan. 8, 2021.
Claims priority of provisional application 63/172,757, filed on Apr. 9, 2021.
Claims priority of provisional application 63/231,291, filed on Aug. 10, 2021.
Prior Publication US 2022/0223512 A1, Jul. 14, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 23/64 (2006.01); H01L 25/065 (2023.01)

CPC H01L 23/49833 (2013.01) [H01L 23/481 (2013.01); H01L 23/642 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/107 (2013.01)]

19 Claims

1. A semiconductor package structure, comprising:

a frontside redistribution layer;

a first semiconductor die disposed over the frontside redistribution layer;

a first capacitor disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die;

a conductive terminal disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer; and

a backside redistribution layer disposed over the first semiconductor die,

wherein the first capacitor is a multi-terminal multi-capacitor structure and is electrically coupled to a second semiconductor die adjacent to the first semiconductor die.