US 12,230,559 B2
Semiconductor device and method of forming micro interconnect structures
Francis J. Carney, Mesa, AZ (US); Jefferson W. Hall, Chandler, AZ (US); and Michael J. Seddon, Gilbert, AZ (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Jun. 5, 2023, as Appl. No. 18/329,347.
Application 17/082,512 is a division of application No. 16/131,462, filed on Sep. 14, 2018, granted, now 10,825,764, issued on Nov. 3, 2020.
Application 18/329,347 is a continuation of application No. 17/082,512, filed on Oct. 28, 2020, granted, now 11,710,691.
Application 16/131,462 is a continuation of application No. 15/218,974, filed on Jul. 25, 2016, granted, now 10,090,233, issued on Oct. 2, 2018.
Claims priority of provisional application 62/219,666, filed on Sep. 17, 2015.
Prior Publication US 2023/0307343 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/498 (2006.01); H01L 21/02 (2006.01); H01L 21/288 (2006.01); H01L 21/304 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/66 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/482 (2006.01); H01L 23/495 (2006.01); H01L 23/544 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 27/14 (2006.01); H01L 27/146 (2006.01); H01L 29/08 (2006.01); H02M 3/158 (2006.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01); H01L 23/367 (2006.01)
CPC H01L 23/49827 (2013.01) [H01L 21/02035 (2013.01); H01L 21/288 (2013.01); H01L 21/304 (2013.01); H01L 21/3065 (2013.01); H01L 21/308 (2013.01); H01L 21/3083 (2013.01); H01L 21/4825 (2013.01); H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 21/67069 (2013.01); H01L 21/6835 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 22/26 (2013.01); H01L 23/3107 (2013.01); H01L 23/3114 (2013.01); H01L 23/481 (2013.01); H01L 23/4822 (2013.01); H01L 23/49503 (2013.01); H01L 23/4951 (2013.01); H01L 23/49541 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H01L 23/544 (2013.01); H01L 23/562 (2013.01); H01L 24/00 (2013.01); H01L 24/05 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 27/14 (2013.01); H01L 27/14683 (2013.01); H01L 29/0847 (2013.01); H02M 3/158 (2013.01); H01L 23/147 (2013.01); H01L 23/15 (2013.01); H01L 23/3677 (2013.01); H01L 23/49816 (2013.01); H01L 27/14625 (2013.01); H01L 27/14685 (2013.01); H01L 2221/68327 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/5446 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05084 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05164 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05172 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06593 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first substrate comprising a first surface and one or more side surfaces substantially perpendicular to the first surface;
a plurality of recesses formed in the one or more side surfaces of the first substrate;
a second substrate comprising a first surface and one or more side surfaces substantially perpendicular to the first surface;
one or more extensions comprised on the one or more side surfaces of the second substrate;
a third substrate comprising a first surface and one or more side surfaces substantially perpendicular to the first surface;
a first conductive layer on the one or more side surfaces of the first substrate;
a second conductive layer on the one or more side surfaces of the second substrate; and
a third conductive layer on the one or more side surfaces of the third substrate;
an interconnect coupled to the first conductive layer of the first substrate and to the second conductive layer of the second substrate;
wherein the second substrate is electrically and mechanically coupled with the first substrate at the one or more extensions.