US 12,230,556 B2
Semiconductor package and method of fabricating the same
Jongyoun Kim, Seoul (KR); Minjun Bae, Hwaseong-si (KR); Hyeonseok Lee, Anyang-si (KR); and Gwangjae Jeon, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 27, 2024, as Appl. No. 18/588,699.
Application 18/588,699 is a continuation of application No. 17/509,224, filed on Oct. 25, 2021, granted, now 11,948,872.
Claims priority of application No. 10-2021-0037518 (KR), filed on Mar. 23, 2021.
Prior Publication US 2024/0203850 A1, Jun. 20, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2023.01); H01L 23/34 (2006.01)
CPC H01L 23/49811 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H01L 23/34 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73204 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern;
a dielectric layer on a sidewall of the under-bump pattern;
an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern; and
a redistribution pattern on a top surface of the under-bump pattern,
wherein the solder terminal is on a bottom surface of the under-bump pattern,
wherein the bottom surface of the under-bump pattern is at a level higher than a level of a bottom surface of the dielectric layer,
wherein the under-bump seed pattern does not extend onto any of a top surface of the dielectric layer and the bottom surface of the under-bump pattern.