US 12,230,553 B2
Semiconductor structure, manufacturing method of semiconductor structure and stacked structure
Luguang Wang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 8, 2022, as Appl. No. 17/647,458.
Application 17/647,458 is a continuation of application No. PCT/CN2021/112066, filed on Aug. 11, 2021.
Claims priority of application No. 202110357894.X (CN), filed on Apr. 1, 2021.
Prior Publication US 2022/0319958 A1, Oct. 6, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a base, comprising a substrate and a dielectric layer, wherein the substrate comprises a front surface and a back surface that are opposite to each other; the dielectric layer is formed on the front surface; the base is provided with a via hole; and the via hole penetrates the substrate from the back surface of the substrate and extends to the dielectric layer;
an insulating layer located on an inner wall surface of the via hole; and
a conductive structure, wherein the conductive structure comprises a first conductive layer and a second conductive layer connected to each other; the first conductive layer is close to a bottom of the via hole, and the second conductive layer is close to a top of the via hole; and a diameter of the first conductive layer is less than that of the second conductive layer;
a barrier layer, wherein the barrier layer is located on a surface of the insulating layer; and there is a gap between the barrier layer and the first conductive layer;
wherein the first conductive layer and the barrier layer are spaced apart, and the second conductive layer is connected to the barrier layer.