	US 12,230,549 B2
	Three-dimensional integrated circuit structures and methods of forming the same
Chia-Min Lin, Hsinchu (TW); Ching-Hua Hsieh, Hsinchu (TW); Chih-Wei Lin, Hsinchu County (TW); Sheng-Hsiang Chiu, Tainan (TW); Sheng-Feng Weng, Taichung (TW); and Yao-Tong Lai, Yilan County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 11, 2022, as Appl. No. 17/717,153.
Application 17/717,153 is a continuation of application No. 16/719,955, filed on Dec. 18, 2019, granted, now 11,309,226.
Prior Publication US 2022/0238407 A1, Jul. 28, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01)

CPC H01L 23/3135 (2013.01) [H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 24/16 (2013.01); H01L 24/24 (2013.01); H01L 25/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/24137 (2013.01)]

20 Claims

1. A three-dimensional integrated circuit (3DIC) structure, comprising:

a semiconductor package, comprising at least one semiconductor die and an encapsulation layer aside the semiconductor die;

a molded underfill layer, surrounding a sidewall of the semiconductor package, wherein a top surface of the molded underfill layer is flushed with a top surface of the encapsulation layer, and a coefficient of thermal expansion of the molded underfill layer is greater than a coefficient of thermal expansion of the encapsulation layer of the semiconductor package, and

a ring component surrounding the semiconductor package.