US 12,230,545 B2
Semiconductor devices including dummy gate dielectric layer and methods of manufacturing thereof
Kuei-Yu Kao, Hsinchu (TW); Chen-Yui Yang, Hsinchu (TW); Hsien-Chung Huang, Hsinchu (TW); Chao-Cheng Chen, Hsinchu (TW); Shih-Yao Lin, New Taipei (TW); Chih-Chung Chiu, Hsinchu (TW); Chih-Han Lin, Hsinchu (TW); Chen-Ping Chen, Toucheng Township (TW); Ke-Chia Tseng, Hsinchu (TW); and Ming-Ching Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 30, 2023, as Appl. No. 18/524,242.
Application 18/524,242 is a continuation of application No. 17/461,184, filed on Aug. 30, 2021, granted, now 11,842,929.
Prior Publication US 2024/0096705 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823468 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of channel layers vertically separated from one another, each of the plurality of channel layers extending along a lateral direction;
a source/drain structure disposed on one side of the plurality of channel layers along the lateral direction;
an active gate structure comprising a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of channel layers;
a first gate spacer extending along a sidewall of the upper portion of the active gate structure;
a dummy gate dielectric layer contacting a bottom surface of the first gate spacer and a top surface of a topmost one of the plurality of channel layers; and
a dummy fin structure interposed between a first set and a second set of the plurality channel layers, the lower portion of the active gate structure being also wrapped around the dummy fin structure, the dummy fin structure having a lower portion and an upper portion, the dummy gate dielectric layer being disposed on a sidewall of at least a portion of the upper portion of the dummy fin structure.