US 12,230,544 B2
Stacked transistors with different channel widths
Kangguo Cheng, Schenectady, NY (US); Lawrence A. Clevenger, Saratoga Springs, NY (US); Balasubramanian S. Pranatharthiharan, Watervliet, NY (US); and John Zhang, Altamont, NY (US)
Assigned to Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed by Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed on Nov. 2, 2022, as Appl. No. 17/979,345.
Application 15/463,155 is a division of application No. 15/339,665, filed on Oct. 31, 2016, granted, now 9,660,028, issued on May 23, 2017.
Application 17/979,345 is a continuation of application No. 16/932,362, filed on Jul. 17, 2020, granted, now 11,538,720.
Application 16/932,362 is a continuation of application No. 16/114,816, filed on Aug. 28, 2018, granted, now 10,741,449, issued on Aug. 11, 2020.
Application 16/114,816 is a continuation of application No. 15/463,155, filed on Mar. 20, 2017, granted, now 10,354,921, issued on Jul. 16, 2019.
Prior Publication US 2023/0298941 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/535 (2006.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823418 (2013.01) [H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/6681 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/786 (2013.01); H01L 29/78696 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a first stack of nanowires above a semiconductor substrate;
a first gate structure over, around, and between the first stack of nanowires;
a second stack of nanowires above the semiconductor substrate;
a second gate structure over, around, and between the second stack of nanowires;
a first source/drain region contacting a first number of nanowires of the first nanowire stack; and
a second source/drain region contacting a second number of nanowires of the second nanowire stack, wherein:
the first number and the second number of contacted nanowires are different;
the first source/drain region is disposed directly on the semiconductor substrate; and
the second source/drain region is disposed on a dielectric region.