US 12,230,542 B2
Method for dicing a semiconductor wafer structure
Shu-Hui Su, Tucheng (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 31, 2022, as Appl. No. 17/709,696.
Prior Publication US 2023/0317521 A1, Oct. 5, 2023
Int. Cl. H01L 21/78 (2006.01); H01L 23/544 (2006.01)
CPC H01L 21/78 (2013.01) [H01L 23/544 (2013.01); H01L 2223/5448 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, the method comprising:
performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate;
performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side; and
performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.