US 12,230,539 B2
Wafer chip scale packaging with ball attach before repassivation
Daiki Komatsu, Beppu (JP); and Makoto Shibuya, Beppu (JP)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 1, 2018, as Appl. No. 16/051,590.
Prior Publication US 2020/0043778 A1, Feb. 6, 2020
Int. Cl. H01L 23/52 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/49 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/538 (2006.01)
CPC H01L 21/76837 (2013.01) [H01L 21/76877 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/5386 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 2924/35 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a conductive structure at least partially above a conductive feature of a wafer;
attaching a solder ball structure to a side of the conductive structure; and
after attaching the solder ball structure to the side of the conductive structure, forming a repassivation layer on a side of the wafer proximate the side of the conductive structure, wherein forming the repassivation layer on the side of the wafer includes:
performing a printing process that forms the repassivation layer on the side of the wafer proximate the side of the conductive structure; and
curing the repassivation layer including heating the wafer while performing the printing process to at least partially cure the repassivation layer.