US 12,230,536 B1
Self-assembled guided hole and via patterning over grating
Florian Gstrein, Portland, OR (US); Eungnak Han, Portland, OR (US); Manish Chandhok, Beaverton, OR (US); and Gurpreet Singh, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,490.
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/7681 (2013.01) [H01L 21/76816 (2013.01); H01L 23/5226 (2013.01); H01L 2221/1036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device (IC) device comprising:
a layer comprising a first material, the layer comprising an active area and an inactive area; and
a plurality of structures formed in the active area of the layer and the inactive area of the layer, the structures comprising a second material different from the first material;
wherein, in at least a portion of the active area, the plurality of structures are arranged in a regular pattern, and in the inactive area, the plurality of structures are arranged in an irregular pattern.