US 12,230,535 B2
Method for fabricating semiconductor device with damascene structure
Wei-Chen Pan, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Mar. 23, 2022, as Appl. No. 17/701,938.
Prior Publication US 2023/0307288 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); G03F 1/38 (2012.01); H01L 21/027 (2006.01)
CPC H01L 21/76807 (2013.01) [H01L 21/0274 (2013.01); H01L 21/76829 (2013.01); G03F 1/38 (2013.01); H01L 2221/1036 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
providing a photomask comprising an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate, wherein the translucent layer comprises a mask opening of via feature which exposes a portion of the mask substrate;
providing a device stack comprising a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer;
forming a pre-process mask layer on the device stack;
patterning the pre-process mask layer using the photomask to form a patterned mask layer comprising a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature, wherein the pre-process mask layer is patterned using the photomask by facing the mask substrate toward the device stack such that the mask substrate is located between the opaque layer and the pre-process mask layer, wherein a thickness of the trench region is less than a thickness of the mask region;
performing a damascene etching process to form a via opening in the first dielectric layer and a trench opening in the second dielectric layer;
removing the patterned mask layer after the via opening and the trench opening are formed, wherein a depth of the via opening is at least equal to a thickness of the first dielectric layer, wherein a depth of the trench opening is equal to a thickness of the second dielectric layer; and
forming a via in the via opening and a trench in the trench opening to configure the semiconductor device;
wherein in beginning of the damascene etching process, the trench region of the patterned mask layer serves as an etching buffer to protect the second dielectric layer;
wherein during the damascene etching process, the first dielectric layer and the second layer under the trench region is temporarily protected by the trench region;
wherein after the damascene etching process, the via opening is formed in the first dielectric layer.