US 12,230,534 B2
Semiconductor device and method of manufacture
Tai-I Yang, Hsinchu (TW); Wei-Chen Chu, Taichung (TW); Yung-Chih Wang, Taoyuan (TW); Chia-Tien Wu, Taichung (TW); Hsin-Ping Chen, Hsinchu County (TW); and Shau-Lin Shue, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/225,249.
Application 17/240,006 is a division of application No. 16/559,450, filed on Sep. 3, 2019, granted, now 10,991,618, issued on Apr. 27, 2021.
Application 18/225,249 is a continuation of application No. 17/240,006, filed on Apr. 26, 2021, granted, now 11,764,106.
Prior Publication US 2023/0369096 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 21/76802 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a conductive line;
an etch stop layer contacting a first portion of a top surface of the conductive line;
a conductive via contacting a second portion of the top surface of the conductive line; and
a first dielectric layer overlying the etch stop layer and disposed between a first portion of a sidewall of the etch stop layer and a first portion of a sidewall of the conductive via.