US 12,230,522 B2
Inline wafer defect detection system and method
Patrick David Noll, Richardson, TX (US); and Suzie Ghidei, Dallas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Dec. 30, 2021, as Appl. No. 17/565,896.
Claims priority of provisional application 63/237,789, filed on Aug. 27, 2021.
Prior Publication US 2023/0072713 A1, Mar. 9, 2023
Int. Cl. H01L 21/67 (2006.01); G06T 7/00 (2017.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01)
CPC H01L 21/67288 (2013.01) [G06T 7/001 (2013.01); H01L 21/78 (2013.01); H01L 22/20 (2013.01); G06T 2207/30148 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit (IC), the method comprising:
processing a semiconductor wafer in a fabrication flow having a sequence of process steps for creating at least one semiconductor die containing the IC, the semiconductor wafer forming a substrate for the IC;
after a targeted process step, performing a wafer inspection of the semiconductor wafer to detect whether the semiconductor wafer is defective after the targeted process step, the wafer inspection comprising an ensemble of image analysis techniques performed on a preprocessed image of the semiconductor wafer generated after completing the targeted process step and preprocessed to remove image artifacts;
responsive to detecting that the semiconductor wafer is defective after completing the targeted process step, determining if the semiconductor wafer is reworkable;
responsive to determining that the semiconductor wafer is reworkable, repeating the targeted process step for the semiconductor wafer after performing a rework process; and
after completing the sequence of process steps, including the targeted process step, singulating the semiconductor die containing the IC for packaging.