US 12,230,503 B2
Semiconductor device with metal gate fill structure
Chung-Liang Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,757.
Application 18/358,757 is a continuation of application No. 17/192,809, filed on Mar. 4, 2021, granted, now 11,728,171.
Claims priority of provisional application 63/044,275, filed on Jun. 25, 2020.
Prior Publication US 2023/0369057 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/306 (2006.01); G06N 20/00 (2019.01); H01L 21/283 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/30604 (2013.01) [G06N 20/00 (2019.01); H01L 21/283 (2013.01); H01L 27/088 (2013.01); H01L 29/0665 (2013.01); H01L 29/4236 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
an interlevel dielectric layer;
a first transistor including:
a first trench formed in the interlevel dielectric layer;
a gate dielectric positioned on sidewalls of the first trench and on a bottom of the first trench;
a first gate electrode, including:
a first gate metal positioned on the gate dielectric at the bottom of the first trench; and
a conductive gate fill material positioned over the first gate metal in the first trench, wherein the conductive gate fill material extends to a higher vertical level within the first trench than the first gate metal, and the first gate metal is between the bottom of the first trench and the conductive gate fill material, does not extend to a same level as the conductive gate fill material with respect to a top of the first trench, and is separated from the conductive gate fill material;
a second transistor including:
a second trench formed in the interlevel dielectric layer;
the gate dielectric positioned on sidewalls of the second trench and on a bottom of the second trench; and
a second gate electrode, including the conductive gate fill material positioned in the second trench above the gate dielectric, the conductive gate fill material of the second transistor being positioned closer to the bottom of the second trench than the conductive gate fill material of the first transistor is positioned to the bottom of the first trench, and the second gate electrode does not include the first gate metal at the bottom of the second trench and between the bottom of the second trench and the conductive gate fill material.