US 12,230,502 B2
Semiconductor package stress balance structures and related methods
Yusheng Lin, Phoenix, AZ (US); Michael J. Seddon, Gilbert, AZ (US); Francis J. Carney, Mesa, AZ (US); Takashi Noma, Ota (JP); and Eiji Kurose, Oizumi-machi (JP)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Oct. 16, 2020, as Appl. No. 17/072,521.
Application 16/702,958 is a division of application No. 15/679,661, filed on Aug. 17, 2017, granted, now 10,529,576, issued on Jan. 7, 2020.
Application 17/072,521 is a continuation in part of application No. 16/861,910, filed on Apr. 29, 2020, granted, now 11,367,619.
Application 16/861,910 is a continuation in part of application No. 16/702,958, filed on Dec. 4, 2019, granted, now 11,328,930.
Application 16/861,910 is a continuation in part of application No. 15/921,898, filed on Mar. 15, 2018, granted, now 10,748,850, issued on Aug. 18, 2020.
Prior Publication US 2021/0035807 A1, Feb. 4, 2021
Int. Cl. H01L 21/56 (2006.01); H01L 21/302 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/12 (2006.01); H01L 23/31 (2006.01)
CPC H01L 21/302 (2013.01) [H01L 21/48 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/12 (2013.01); H01L 23/3185 (2013.01); H01L 24/04 (2013.01); H01L 24/26 (2013.01); H01L 2224/94 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor die comprising a first side and a second side, the first side of the semiconductor die comprising one or more electrical contacts;
a layer of metal coupled directly to the second side of the semiconductor die; and
only a single stress balance structure coupled directly to and around the one or more electrical contacts,
wherein the single stress balance structure is a continuously formed structure;
wherein the semiconductor die comprises a thickness between 0.1 microns and 125 microns; and
wherein the single stress balance structure is directly coupled to only the semiconductor die at the first side and a plurality of sidewalls.