US 12,230,439 B2
Inductor tuning in superconducting circuits
Paige Frederick, Seattle, WA (US); Kenneth Reneris, Kirkland, WA (US); Matus Lipka, Kirkland, WA (US); Jason Lee, Savannah, GA (US); and Jamie Kuesel, Redmond, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Apr. 30, 2021, as Appl. No. 17/246,497.
Application 17/246,497 is a continuation in part of application No. 17/235,798, filed on Apr. 20, 2021, abandoned.
Prior Publication US 2024/0282495 A1, Aug. 22, 2024
Int. Cl. H01F 7/06 (2006.01)
CPC H01F 7/064 (2013.01) 20 Claims
OG exemplary drawing
 
1. A computer system comprising:
one or more processors; and
a non-transitory computer readable storage medium coupled to the one or more processors and having stored thereon program code executable by the one or more processors to:
determine an inductance for each of a plurality of inductors of a circuit, the plurality of inductors routed between Josephson junctions,
determine an amount of coupled flux between inductors of the plurality of inductors, and
adjust widths along portions of plurality of inductors based on the inductance, the amount of coupled flux, and inductance requirements of the Josephson junctions.