US 12,230,362 B2
Memory component with programmable data-to-clock ratio
Torsten Partsch, San Jose, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 25, 2024, as Appl. No. 18/646,059.
Application 18/646,059 is a continuation of application No. 18/216,513, filed on Jun. 29, 2023, granted, now 11,996,164.
Application 18/216,513 is a continuation of application No. 17/432,064, granted, now 11,735,237, issued on Aug. 22, 2023, previously published as PCT/US2020/019606, filed on Feb. 25, 2020.
Claims priority of provisional application 62/811,414, filed on Feb. 27, 2019.
Prior Publication US 2024/0404571 A1, Dec. 5, 2024
Int. Cl. G11C 7/22 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 2207/2227 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated-circuit memory component (memory IC) comprising:
a clock input to receive a clock signal;
a programmable register;
a command interface to receive a register-programming command synchronously with respect to the clock signal and, in response to the register-programming command, to store within the programmable register a control value that specifies one of a plurality of operating modes; and
a synchronous data interface to:
sample a write data signal in a first mode to generate a first quantity of write data bits per cycle of the clock signal if the control value specifies a first operating mode;
sample the write data signal in a second mode to generate a second quantity of write data bits per cycle of the clock signal if the control value specifies a second operating mode, the second quantity of data bits exceeding the first quantity of data bits; and
transmit a read data signal synchronously with respect to the clock signal.