US 12,230,361 B2
Acceleration of in-memory-compute arrays
Paolo Di Febbo, Redwood City, CA (US); Mohamed H. Abu-Rahma, Mountain View, CA (US); Jelam K. Parekh, Milpitas, CA (US); Yildiz Sinangil, Campbell, CA (US); Mohammad Ghasemzadeh, San Jose, CA (US); Anthony Ghannoum, Santa Clara, CA (US); and Chaminda N. Vidanagamachchi, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 3, 2023, as Appl. No. 18/346,565.
Application 18/346,565 is a continuation of application No. 17/406,817, filed on Aug. 19, 2021, granted, now 11,694,733.
Prior Publication US 2024/0005972 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); H03M 1/82 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/106 (2013.01); G11C 7/1087 (2013.01); H03M 1/82 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an in-memory compute circuit that includes:
a plurality of memory cells, arranged in one or more columns, and configured to store respective weight values;
a plurality of digital-to-analog converters (DACs), wherein a particular DAC of the plurality of DACs is coupled to a respective row of the one or more columns of memory cells and is configured to generate a particular output voltage level using a particular digital input value to the respective row; and
wherein the in-memory compute circuit is configured to:
generate an adjusted output voltage level using the particular output voltage level and a respective weight value stored in a particular memory cell in the respective row;
generate an accumulated voltage level indicative of an accumulated output value of a particular column of the one or more columns.