US 12,230,360 B2
Controlling memory module clock buffer power in a system with dual memory clocks per memory module
Isaac Q. Wang, Austin, TX (US); and Lee B. Zaretsky, Nazare (PT)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by DELL PRODUCTS L.P., Round Rock, TX (US)
Filed on Feb. 28, 2023, as Appl. No. 18/176,284.
Application 18/176,284 is a continuation in part of application No. 17/962,387, filed on Oct. 7, 2022.
Prior Publication US 2024/0119980 A1, Apr. 11, 2024
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 7/225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An information handling system, comprising:
a host processing system including a first memory clock and a second memory clock; and
a memory module including:
a first rank of memory devices of a first sub-channel of memory devices;
a first rank of memory devices of a second sub-channel of memory devices; and
a clock buffer device including:
a first clock input coupled to the first memory clock;
a first phase-locked loop (PLL) selectably coupled to the first clock input;
a second clock input coupled to the second memory clock; and
a second PLL selectably coupled to the second clock input;
wherein the clock buffer device is configured:
in a first mode, to couple the first clock input via the first PLL to the first rank of memory devices of the first sub-channel and via the first PLL to the first rank of memory devices of the second sub-channel;
in a second mode, to couple the first clock input directly to the first rank of memory devices of the first sub-channel and directly to the first rank of memory devices of the second sub-channel;
in a third mode, to couple the first clock input via the first PLL to the first rank of memory devices of the first sub-channel and to couple the second clock input signal via the second PLL to the first rank of memory devices of the second sub-channel; and
in a fourth mode, to couple the first clock input directly to the first rank of memory devices of the first sub-channel and to couple the second clock input directly to the first rank of memory devices of the second sub-channel.