US 12,230,359 B2
Semiconductor device
Meng-Sheng Chang, Hsinchu County (TW); Yao-Jen Yang, Hsinchu County (TW); Yih Wang, Hsinchu (TW); and Fu-An Wu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Feb. 3, 2023, as Appl. No. 18/164,282.
Application 18/164,282 is a division of application No. 16/713,967, filed on Dec. 13, 2019, granted, now 11,600,626.
Prior Publication US 2023/0189513 A1, Jun. 15, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 5/06 (2006.01); G11C 8/08 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 23/522 (2006.01); H01L 23/525 (2006.01); H10B 20/25 (2023.01)
CPC G11C 7/1096 (2013.01) [G11C 5/063 (2013.01); G11C 7/1069 (2013.01); G11C 8/08 (2013.01); G11C 17/165 (2013.01); G11C 17/18 (2013.01); H01L 23/5226 (2013.01); H01L 23/5252 (2013.01); H10B 20/25 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of anti-fuse cells comprising:
a first active area;
a first gate and a second gate that are separate from each other along a first direction, wherein the first gate and the second gate extend to cross over the first active area;
at least one first gate via coupled to the first gate and disposed directly above the first active area;
at least one second gate via coupled to the second gate; and
a bit line coupled to the first active area and crossing over the first active area along a second direction perpendicular to the first direction,
wherein the first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.