US 12,230,353 B2
Bridge chip, semiconductor storage device, and memory system
Mikio Shiraishi, Yokohama Kanagawa (JP)
Assigned to KIOXIA CORPORATION
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 3, 2023, as Appl. No. 18/177,955.
Claims priority of application No. 2022-100525 (JP), filed on Jun. 22, 2022.
Prior Publication US 2023/0420004 A1, Dec. 28, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01); H10B 80/00 (2023.01)
CPC G11C 7/10 (2013.01) [G11C 7/22 (2013.01); G11C 16/10 (2013.01); G11C 16/32 (2013.01); H10B 80/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A bridge chip comprising:
a first selection circuit configured to determine a first output destination of input data and an input flag, the input flag indicating whether the input data is valid or invalid, based on a first selection signal;
a second selection circuit configured to determine a second output destination of the input data and the input flag output from the first selection circuit, based on a second selection signal; and
a control circuit configured to:
generate the first selection signal and the second selection signal, and
output the first selection signal and the second selection signal to the first selection circuit and the second selection circuit, respectively.