	US 12,230,352 B2
	Memory device, memory cell read circuit, and control method for mismatch compensation
Ku-Feng Lin, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 23, 2023, as Appl. No. 18/518,578.
Application 18/518,578 is a continuation of application No. 18/084,570, filed on Dec. 20, 2022, granted, now 11,854,650.
Application 18/084,570 is a continuation of application No. 17/035,609, filed on Sep. 28, 2020, granted, now 11,574,657, issued on Feb. 7, 2023.
Prior Publication US 2024/0087617 A1, Mar. 14, 2024
Int. Cl. G11C 7/06 (2006.01)

CPC G11C 7/06 (2013.01)

20 Claims

1. A memory device, comprising:

a memory array with a memory cell and a reference memory cell; and

a memory cell read circuit, wherein the memory cell read circuit comprising:

a first branch, comprising a first circuit device, configured to output a first voltage to the reference memory cell in a trimming operation;

a second branch, comprising a second circuit device, configured to output a second voltage to the memory cell in the trimming operation,

wherein the first circuit device comprises a first transistor and a plurality of second transistors coupled to the first transistor, a control terminal of the first transistor and control terminals of the plurality of second transistors are biased by a fixed clamp voltage, and

wherein the second circuit device comprises a third transistor and a plurality of fourth transistors that are coupled to the third transistor, wherein a control terminal of the third transistor and control terminals of the plurality of fourth transistors are biased by the fixed clamp voltage,

wherein a transistor width of the first transistor is greater than a transistor width of each of the plurality of second transistors, and, a transistor width of one of the plurality of second transistors is different from a transistor width of another one of the plurality of second transistors,

wherein each of the plurality of second transistors, when individually conducted, is configured to adjust a total transistor size of conducted transistors in the first circuit device by a second percentage of the total transistor size of the conducted transistors in the first circuit device,

the plurality of second transistors include a first number of conducted trimming transistors, and

the first number of conducted trimming transistors is determined according to the second percentage of the total transistor size of the conducted transistors in the first circuit device and a change of the total transistor size of the conducted transistors in the first circuit device, wherein the change of the total transistor size of the conducted transistors in the first circuit device is determined according to the mismatch between the first voltage and the second voltage.