a memory array comprising a plurality of memory cell blocks arranged in rows and columns, where the memory cell blocks are clustered into a defined number of memory cell blocks along the row, each cluster is connected to a respective local reference line;

a plurality of sense amplifiers connected to the respective memory cell blocks;

at least one dummy memory cell block additionally arranged to each cluster of memory cell blocks, connected to a main reference line; and

at least one transistor arranged in between the local reference line of each cluster of memory cell blocks and the main reference line,

wherein the transistor is configured to receive an input signal from the dummy memory cell block, thereby performing power gating of the respective cluster of memory cell blocks based on the input signal from the dummy memory cell block.